The present invention is related generally to an integrated circuit, and more particularly to a voltage level shifter that may be used in various integrated circuits including a LCD controller to reduce power consumption.
A voltage level shifter is a circuit that allows a digital signal to be level shifted from a low supply voltage to a high supply voltage. As the minimum feature size of integrated circuits further decreases, the supply voltage for the core logic section of the integrated circuit (IC) is reduced further to around 1.0 volt or a lower voltage level. However, the supply voltage for the input/output (IO) section of the integrated circuit must be maintained at a higher level (3.3 volts or much higher voltage) to assure adequate signal-to-noise ratio and compatibility with other devices. For example, in a liquid crystal display (LCD) device, an input signal applied to LCD controller ICs is around 3 volts while 20 to 40 volt signals are required to turn on the thin film transistors (TFTs) used in the LCD panel. In this case, a voltage level shifter is applied for the voltage conversion purpose.
FIG. 2A illustrates a conventional voltage level shifter 200. The voltage level shifter 200 uses four types of transistors. Low voltage NMOS and PMOS transistors (not shown) are used in the low supply voltage VDD 202 of the inverter 220. High voltage NMOS transistors 217, 223 and high voltage PMOS transistors 203, 205 are used in the high supply voltage VDDPST 201 section. The low voltage transistors have a thinner gate oxide than that of the high voltage transistors. In addition, the high voltage transistors have a threshold voltage higher than that of the low voltage transistors by typically 0.2-0.4 volts to reduce leakage current during the operation of the voltage level shifter 200.
In the conventional voltage level shifter 200, one common drawback is its poor leakage current characteristic. Leakage currents 219, 221 flow from the high supply voltage VDDPST 201 to ground VSS 203, particularly while the core voltage VDD is turned off during a power saving mode, thereby degrading the power consumption performance of the circuit 200. When the core supply voltage VDD 202 is turned off, the transistors coupled to the core supply voltage VDD are left in a floating state, thereby becoming unstable enough to trigger a leakage path from the node ND207 or ND 209 to ground VSS 203 through the transistors 217 and/or 223. Increased leakage current is also observed when the core supply voltage VDD 202 is ramping up.
Referring to FIG. 2A, the conventional voltage level shifter 200 uses an inverter 220 and a differential pair made up of transistors 203, 205, 217, and 223. If a low supply voltage or core supply voltage VDD 202 swings between about 0 volt and 1.2 volts and a high voltage supply or IO supply voltage VDDPST 201 swings between 0 volt and 3.3 volts, the function of the voltage level shifter 200 is to convert a low voltage input signal IN 215 swinging between 0 volt and 1.2 volts (VDD) to a high voltage output signal OUTPUT 211 swinging between 0 volt and 3.3 volts (VDDPST) at an output node disposed between transistor 203 and transistor 223.
When the input signal IN 215 is logic low (VSS), NMOS transistors 217 and PMOS transistor 203 are turned on, causing the output signal OUTPUT 211 to become logic high (VDDPST 201). If the input signal IN 215 is logic high (VDD), NMOS transistors 223 and PMOS transistor 205 are turned on, causing the output signal OUTPUT 211 to be pulled down to logic low (VSS).
FIG. 2B illustrates a simplified schematic of a CMOS buffer circuit 250 where the voltage level shifter 251 is applied for interfacing a low voltage (core voltage VDD) circuit and a high voltage (IO supply voltage VDDPST) circuit in the LCD controller IC as shown in FIG. 1A. The CMOS buffer circuit 250 comprises a voltage level shifter block 252, a decoding circuit block 254, and a driver circuit 256, respectively. Since the conventional voltage level shifter 200 and the CMOS buffer circuit 250 are well known to those in the art, a detailed description of their operation is omitted.
As briefly described above, one drawback of the conventional voltage level shifter circuit 200 is its poor leakage current performance, particularly when the core supply voltage VDD is turned off during a power saving mode, thereby degrading the power consumption characteristic of the circuit. The present invention recognizes the drawback of the conventional art and provides an improved voltage level shifter.